Latch vs flip-flop, setup/hold time and metastability

One is level-sensitive and the other is edge-triggered.

Model answer.

Latch vs flip-flop

• A latch is level-sensitive. A D latch is transparent while its enable is active: the output follows the input. When the enable goes inactive, the last value is held.
• A flip-flop is edge-triggered. A D flip-flop samples D only at the active clock edge (for example, the rising edge) and holds that value until the next edge. A common implementation is two latches in master-slave arrangement on opposite clock phases.
• Most synchronous designs use flip-flops, because edge-triggering makes timing analysis predictable and avoids signals racing through several transparent stages in one clock phase.

Setup and hold time

• Setup time (t_su): the minimum time the D input must be stable before the clock edge.
• Hold time (t_h): the minimum time D must stay stable after the clock edge.
• If either is violated, the flip-flop may not capture the correct value. Setup violations are fixed by slowing the clock or shortening the logic path; hold violations are fixed by adding delay to the path, because changing the clock frequency does not help.

Metastability
If D changes inside the setup-hold window, the flip-flop can enter a metastable state: its output sits at an intermediate voltage or oscillates for an unpredictable time before settling to 0 or 1. Downstream logic may read it differently, which causes system failures.

It typically happens when a signal crosses from one clock domain to another, or when an asynchronous input such as a push-button or an external interrupt line enters a synchronous system.

Reducing the risk

• Use a two-flip-flop synchroniser: the first flip-flop may go metastable, but it has one full clock period to settle before the second samples it. This lowers the failure probability dramatically, although it never makes it exactly zero.
• Use handshakes or asynchronous FIFOs for multi-bit data crossing clock domains, and Gray code for counters crossing domains.

Likely follow-up. "Why not synchronise a multi-bit bus bit by bit?" Different bits may resolve on different clock cycles, giving a value that never existed.